Why is there a minimum clock speed for CPUs

This is a fairly interesting question with a simple answer, but you will not find satisfying search results from a simple search.

The question is, why is there a minimum clock rate for CPUs. This can be raised from thinking about many things, such as underclocking, lowering idle power consumption, etc. Generally, there is a positive correlation between CPU clock speed and power consumption, so the natural assumption is that lowering clocks lead to less power consumption, which is what CPUs do during idle. Yet, it is generally not possible to go too low, something like a 1GHz clock on a modern 3GHz chip is not possible.

Yet this was actually possible in certain CPUs. For example the Zilog Z80 can be supplied a manual clock, as seen in this video where the clock is a keyboard switch. Most breadboard computers built out of logic gates also have this capability, as seen in this video by Ben Eater where his clock has a manual override he uses during debugging.

So, why can't AMD and Intel let us have this capability?

Partial answers

Here are some partial answers that do not address the actual problem.

First answer: the registers need to be refreshed! Memory in the form of DRAM needs to be refreshed since they store charge in capacitors. Registers are probably some kind of DRAM since DRAM is much faster than SRAM. However, let's just assume we put all registers away in some other place that can be refreshed on its own and the rest of the CPU uses some other clock. Or, maybe you can use SRAM for registers and make a slower version of the chip, very useful for mobile applications if that sacrifice allows for extremely low clocks during idle. Why can't we do that?

Second answer: the system would become unresponsive. Key word in the original question is "idle". The CPU would perhaps only sleep for a few microseconds, and not forever, like how C-States already work. You can just set up timer interrupts to wake it 100 times a second or something.

The answer

The answer is actually due to how the CPU is implemented. In the most basic models of logic gates that we are taught, we have been told that logic gates basically take a set of inputs and produce an output. For example an AND gate will take in two inputs and return HIGH iff both are HIGH. In this model, the logic gates are completely stateless. State can be delegated to the memory and registers. This is termed static logic.

Modern CPUs actually use dynamic logic. In dynamic logic, a clock is not only present, but absolutely required. In dynamic logic, for half the clock the transistors are initialized and the other half of the clock they then settle into the correct computed output. The result is stored in a small capacitor.

This seems absolutely stupid, like it was fine at first and these engineers are just adding capacitors and clocks and causing more problems.

It is actually fairly interesting because it seems like it's not solving anything by adding capacitors, but the capacitor actually saves many more transistors from the final logic gate. The Wikipedia has a comparison between an example NAND gate. The fewer transistors, and the different types of transistors used [^hole], means that dynamic logic is a lot faster than static logic.

The transistor type affects the switching speed of the transistor. Holes are the majority carriers in p-type semiconductors, i.e. current is carried by holes. Hole mobility is 2 to 3 times slower than electron mobility in silicon, so current travels this much slower in them. Therefore, we generally prefer to use n-type over p-type transistors when switching speed is a concern.

Originally logic gates were only implemented in PMOS. They were easier to manufacture, although I don't know the reason why. Later NMOS was made possible. The problem with PMOS and NMOS only logic is that they require resistors to operate. For reasons I won't talk about, NMOS only produces a strong 0 and PMOS only produces a strong 1. Therefore you need a pull up or pull down resistor to produce the 1 or 0 signal that they cannot reliably create. The resistors are pretty bad because they slowly bleed current away even when the circuit is not doing anything, causing power and heat problems. They are also claimed to be slow to switch, although I'm not sure about this because usually the resistors are implemented as MOSes themselves.

Therefore, enter CMOS, which stands for Complementary MOS. CMOS uses both PMOS and NMOS in a same unit connected somewhat like end to end. Again for certain reasons doing things this way fixes a lot of the problems with just using plain NMOS or PMOS. So now the NMOS is acting as a pull down for the PMOS and the PMOS is acting as a pull up for the NMOS.

The idea behind dynamic logic is to use the parasitic capacitance of the capacitor to replace the need for the pull up load. The capacitor is always charged up on the first half of the clock, and the next half of the clock is for the NMOSes to evaluate and the reading out of the result. Thus you effectively save around half the number of transistors, and can also do away with almost all of the PMOS transistors. Therefore it's faster.

And also, that's why the clock is needed, and that's why it's just like this.

You're just using big words

Let's give a real world example from the past decade to illustrate that it's just something I'm making up.

Intel has once released the Nehalem series of chips that uses static logic, with power consumption being a big selling point (see slides in Anandtech article). Anandtech claims anywhere from 15-25% improvement in performance per watt over its predecessor. These docs from Redhat claims that this "recent" microarchitecture of Nehalem has a new C-State, C6 that can bring voltage to near 0 but realistically reduces power consumption by around 80-90%.

So there you go.